1. Field
Embodiments of the present invention relate to a semiconductor package and a method of fabricating the same, and more particularly, to a stack type power module and a method of fabricating the same.
2. Description of the Related Art
In general, when a semiconductor package is fabricated, a semiconductor chip or a plurality of semiconductor chips is mounted on a lead frame or a printed circuit board (PCB), and sealed for protection reasons using a sealant, e.g., an epoxy molding compound (EMC). The semiconductor package is mounted on a mother board or a system PCB.
In line with requirements for high speed, large storage capacity, and high integration of electronic devices, demands for compact, light, and inexpensive power devices have increased. To satisfy such demands, a plurality of semiconductor chips is mounted in a semiconductor package to constitute a stack type power module. However, in such a stack type power module, chips are generally connected to a lead frame or the like using wire bonding. Thus, the possibilities to reduce the size of the stack type power module are limited.
FIG. 1 is a cross-sectional view of a conventional power module package disclosed in Korean Patent Publication Gazette No. 2002-0095053, entitled “Power Module Package Having Improved Heat Emission Capability and Method of Fabricating the Same.” Referring to FIG. 1, the conventional power module package has a structure in which a plurality of power device chips 22 and a plurality of control device chips 30 are mounted on a lead frame 40 and sealed using a sealant 50. The lead frame 40 is divided into portions A and B, which are different from each other and in which the power device chips 22 and the control device chips 30 are respectively mounted. In other words, a thermal substrate 10 is disposed under the portion A of the lead frame 40 to emit heat generated from the power device chips 22. The thermal substrate 10 is attached to the portion A of the lead frame 40 through a solder paste 12.
In the conventional power module package, the power device chips 22 or the control device chips 30 are mounted on the lead frame 40 through metal wires 24 formed of Au or Al using a bonding method. Thus, a space for wire bonding must be secured. Thus, the possibility to reduce the size of the conventional power module package is limited. Also, since wire bonding is used, the wires may be cut or an operation characteristic of the conventional power module package may be deteriorated due to a long length of the wires.
FIG. 2 is a cross sectional view of another conventional power module package disclosed in U.S. Pat. No. 5,703,399, entitled “Semiconductor Power Module.” Referring to FIG. 2, the conventional power module package has a structure in which a plurality of power device chips 5a and a plurality of control device chips 4a are mounted on a lead frame 3, and a thermal substrate 1 is disposed under the lead frame 3. A sealant for sealing the power device chips 5a and the control device chips 4a is divided into upper and lower sealants 7 and 2. The lower sealant 2 is formed of a highly thermal conductive material. A resistive component 5b is disposed on the left side of the power device chips 5a, and the conventional power module package is divided into portions A and B in which the power device chips 5a and the control device chips 4a are respectively mounted. Here, 6A and 6B are metal wires.
In the conventional power module package of FIG. 2, the power device chips 5a and the control device chips 4a are mounted on the lead frame 3 using wire bonding as described above. Thus, like in the case of the conventional power module package of FIG. 1, the possibility to reduce the size of the conventional power module package of FIG. 2 is limited. Also, since the upper and lower sealants 7 and 2 are formed of different materials, a sealing process is complicated. Since the lower sealant 2 emits heat, the conventional power module package is disadvantageous in view of the material and thickness of the lower sealant 2.